library ieee;
use ieee.std_logic_1164.all;

entity tb_memoria is
end tb_memoria;

architecture a_tb_memoria of tb_memoria is

	component memoria
		port(
			CE_neg     : in std_logic;
			entrada_REM: in std_logic_vector (3 downto 0);
		   saida_bw   : out std_logic_vector(7 downto 0)
		);
	end component;

   for memoria_0: memoria use entity work.memoria;
   
	signal erro : boolean := false; -- para parar a simulação
 
  	signal tb_ce_not: std_logic := '1';
 	signal tb_entrada_rem: std_logic_vector (3 downto 0) := "0000";
 	signal tb_saida_bw: std_logic_vector (7 downto 0);
 
 	begin
  	memoria_0: memoria port map (tb_ce_not,tb_entrada_rem,tb_saida_bw);
  
	tb_ce_not <= '0' after 160 ns,
            	 '1' after 180 ns,
            	 '0' after 200 ns;

	tb_entrada_rem <= "0001" after 10 ns, -- zera os 16 enderecos de memoria
                	   "0010" after 20 ns,
                 	   "0011" after 30 ns,
                	   "0100" after 40 ns,
                	   "0101" after 50 ns,
                	   "0110" after 60 ns,
                	   "0111" after 70 ns,
                	   "1000" after 80 ns,
                	   "1001" after 90 ns,
                	   "1010" after 100 ns,
                	   "1011" after 110 ns,
                	   "1100" after 120 ns,
                	   "1101" after 130 ns,
                	   "1110" after 140 ns,
                	   "1111" after 150 ns, 
                	   "0011" after 160 ns, -- endereco 3
                	   "1100" after 170 ns, -- endereco 12
                	   "0011" after 180 ns,
                	   "0111" after 190 ns,
                	   "1011" after 200 ns,
                	   "0011" after 210 ns; -- endereco 3
	
	process
	begin
	
    	wait for 165 ns;
    	if(not tb_saida_bw="00101100") then -- verifica se leu endereco 3
    		erro <= true;
    	end if;
    	
    	wait for 10 ns;
    	if(not tb_saida_bw="00100000") then -- verifica se leu endereco 12
    		erro <= true;
    	end if;
    	    	
    	wait for 40 ns;
    	if(not tb_saida_bw="00101100") then -- verifica se leu endereco 3
    		erro <= true;
    	end if;
    	
  	  	assert false report "### Simulação encerrada com sucesso!" severity failure;
  	
	end process;
  
  	assert not erro report "### ERRO!" severity failure;
  	
end a_tb_memoria; 
